The present invention relates to a memory macro and a semiconductor integrated circuit device (LSI: Large Scale Integrated circuit) using the memory macro, and in particular relates to the memory macro and the semiconductor integrated circuit device which are favorably utilized for fault detection of an address selection circuit.
In international standards (for example, ISO26262) for functional safety regarding electric and electronic components of automobiles, fault detection in operation for address selection has come to be requested to a memory such as an SRAM (Static RandomAccess Memory) and so forth in addition to fault detection on the data side. Although so far real time fault detection has been possible by using an error detection (ECC: Error Correction Code) circuit, when a fault has occurred in address selection, it is difficult to detect the fault.
In Japanese Unexamined Patent Application Publication No. 2007-257791, a semiconductor memory device with redundant function which is provided by an ECC memory by changing the configuration of the ECC memory is disclosed. In which address in the memory a defective bit is present is detected in advance, this data is stored as defective address information, and when actually accessing the memory, the relief measures are taken by comparing an address signal which is input with the stored defective address information and replacing the defective bit of the defective address concerned with a redundant bit.